processor-based electronic systems generally include a processor, a memory and one or more devices external to the processor. Typically, the devices communicate with the processor through an external bus. In some of these systems, one or more of these external devices can access the memory. FIG. 1 is a block diagram of an exemplary system 100 in which external devices may access the memory. The system 100 includes a host or processor 102 with an internal or "level one" cache 104. The host 102 is also connected to an external or "level two" cache 106 and a main memory 108. The level one cache 104, the level two cache 106 and the main memory 108 form part of the memory 110 for the system 100.
The host 102 is connected to a bus 120. Several devices 122.sub.1 -122.sub.N are also connected to the bus 120. In this conventional system, the devices 122.sub.1 -122.sub.N may access the memory 110 via the bus 120. In many conventional bus protocols, memory access transactions by an external device "stalls" the bus 120 until the memory access transaction completes. This type of bus protocol is referred to herein as a connection-oriented bus protocol such as, for example, the peripheral component interface (PCI) local bus protocol. For example, using the PCI local bus protocol in the system 100, if a memory read transaction by the external device 122.sub.1 causes a cache miss (i.e., misses the caches 104 and 106), the host 102 must make a memory request from the main memory 108. As a result, the host 102 is required to provide wait states on the bus 120 while accessing the main memory 108, delaying the bus transaction. This delay, referred to herein as host initial data latency, in receiving a first data word in response to a memory read request after a cache miss typically causes a significant decrease in the bandwidth of the bus 120.
In addition to a standard cache miss, because the PCI local bus protocol allows burst memory transactions of unlimited length, memory access transactions may cross a cacheline boundary. A memory transaction that crosses a cacheline boundary typically causes a cache miss so that cache coherency can be maintained. Consequently, due to the host initial data latency, memory access transactions that cross a cacheline boundary also significantly decrease the bandwidth of the bus 120. Accordingly, there is a need for a memory access circuit that avoids the above host initial data latency problem, thereby increasing the bandwidth of the bus 120 during memory access transactions.